{"id":58635,"library":"riscv-rt","title":"riscv-rt","description":"Minimal runtime / startup for RISC-V CPU's.","status":"active","version":"0.18.0","language":"rust","source_language":null,"source_url":"https://github.com/rust-embedded/riscv","tags":["riscv","embedded","startup","runtime","no-std"],"install":[{"cmd":"# Cargo.toml\n[dependencies]\nriscv-rt = \"0.18.0\"","lang":"toml","label":"Cargo.toml"},{"cmd":"cargo add riscv-rt","lang":"bash","label":"cargo add"}],"dependencies":[],"imports":[{"symbol":"entry","correct":"use riscv_rt::entry;"}],"quickstart":{"code":"#![no_std]\n#![no_main]\n\nuse riscv_rt::entry;\n\n#[entry]\nfn main() -> ! {\n    loop {}\n}","lang":"rust","description":"Define the entry point for a RISC-V bare-metal program."},"warnings":[{"fix":"Use a RISC-V target triple (e.g., riscv32imac-unknown-none-elf) and provide a memory.x file.","message":"Requires a RISC-V target and linker script; not for standard environments.","severity":"gotcha","affected_versions":">=0.0.0"}],"env_vars":null,"search_vec":"'cpu':11 'embed':14 'minim':4 'no-std':17 'risc':9 'risc-v':8 'riscv':2,13 'riscv-rt':1 'rt':3 'runtim':5,16 'startup':6,15 'std':19 'v':10","created_at":"2026-06-16T16:33:00.132524+00:00","updated_at":"2026-06-16T16:33:00.132524+00:00","problems":[],"ecosystem":"crates","meta_description":null,"install_score":null,"quickstart_score":null,"quickstart_tag":null,"pypi_latest":null,"cli_name":null,"cli_version":null,"type":"library","homepage":"https://github.com/rust-embedded/riscv","github":"https://github.com/rust-embedded/riscv","docs":"https://docs.rs/riscv-rt/","changelog":null,"pypi":null,"npm":null,"openapi_spec":null,"status_page":null,"smithery":null,"categories":["other"],"base_url":null,"auth_type":null,"provenance":{"verified_status":null,"verified_at":null,"last_verified":"2026-06-16","next_check":"2026-12-13","install_tag":null}}